/* --------------------------------------------------------
/* -                                                      -
/* -    general.def                                       -
/* -                                                      -
/* -   Definitions for PIC16C84                           -
/* -                                                      -
/* -   This file is included by all PICs                  -
/* -                                                      -
/* -                                            (koji)    -
/* -                                                      -
/* --------------------------------------------------------


#print	"CPU Type PIC16C84\n"

#MAXROMSIZE .1024
#AUTO_MIN_ADDRESS	0Ch
#AUTO_MAX_ADDRESS	2Fh
#DATA_MEM_SIZE		.64

/* configuration fuse

#DEF	CNF_COM1_ADR	0x2000
#DEF	CNF_COM2_ADR	0x2001
#DEF	CNF_COM3_ADR	0x2002
#DEF	CNF_COM4_ADR	0x2003
#DEF	CNF_FUSE_ADR	0x2007

#CNF	CNF_COM1_ADR	'K'
#CNF	CNF_COM2_ADR	'O'
#CNF	CNF_COM3_ADR	'J'
#CNF	CNF_COM4_ADR	'I'
#CNF	CNF_FUSE_ADR	0b00000000010010
/*     bit4:Code Protect=off bit3:PoWer up Timer=off bit2:WDT=off bit1,0:X'tal=HS

#DEF	RESET_VECTOR	0x0000
#DEF	INT_VECTOR		0x0004

/* -------------------------------    Achtung!!!!------------   */
/* Logic of PWT is opposite, 
/*        PWT:on  PWT:off
/* 16C84    1        0
/* 16F84    0        1



/* define
/* PAGE 0
#DEF	IND0	0x00
#DEF	TMR0	0x01
#DEF	PCL	0x02
#DEF	STATUS	0x03
#DEF	FSR	0x04
#DEF	PORTA	0x05
#DEF	PORTB	0x06
#DEF	EEDATA	0x08
#DEF	EEADR	0x09
#DEF	PCLATH	0x0A
#DEF	INTCON	0x0B
/* PAGE 1
#DEF	OPTION	0x81
#DEF	TRISA	0x85
#DEF	TRISB	0x86
#DEF	EECON1	0x88
#DEF	EECON2	0x89


/* destination register
#DEF	WREG	0
#DEF	BACK	1

/* STATUS BITS
#BITDEF	STATUS.CARY	STATUS	0
#BITDEF	STATUS.DC	STATUS	1
#BITDEF	STATUS.ZERO	STATUS	2
#BITDEF	STATUS.PD	STATUS	3
#BITDEF	STATUS.TO	STATUS	4
#BITDEF	STATUS.RP0	STATUS	5
#BITDEF	STATUS.RP1	STATUS	6
#BITDEF	STATUS.IRP	STATUS	7
#BITDEF	CARY		STATUS	0
#BITDEF	DC			STATUS	1
#BITDEF	ZERO		STATUS	2
#BITDEF	PD			STATUS	3
#BITDEF	TO			STATUS	4
#BITDEF	RP0			STATUS	5
#BITDEF	RP1			STATUS	6
#BITDEF	IRP			STATUS	7
/* INTCON BITS
#BITDEF	INTCON.RBIF	INTCON	0
#BITDEF	INTCON.INTF	INTCON	1
#BITDEF	INTCON.TOIF	INTCON	2
#BITDEF	INTCON.RBIE	INTCON	3
#BITDEF	INTCON.INTE	INTCON	4
#BITDEF	INTCON.TOIE	INTCON	5
#BITDEF	INTCON.EEIE	INTCON	6
#BITDEF	INTCON.GIE	INTCON	7
#BITDEF	RBIF		INTCON	0
#BITDEF	INTF		INTCON	1
#BITDEF	TOIF		INTCON	2
#BITDEF	RBIE		INTCON	3
#BITDEF	INTE		INTCON	4
#BITDEF	TOIE		INTCON	5
#BITDEF	EEIE		INTCON	6
#BITDEF	GIE			INTCON	7
/* OPTION BITS
#BITDEF	OPTION.PS0		OPTION	0
#BITDEF	OPTION.PS1		OPTION	1
#BITDEF	OPTION.PS2		OPTION	2
#BITDEF	OPTION.PSA		OPTION	3
#BITDEF	OPTION.RTE		OPTION	4
#BITDEF	OPTION.RTS		OPTION	5
#BITDEF	OPTION.INTEDG	OPTION	6
#BITDEF	OPTION.RBPU		OPTION	7
#BITDEF	PS0				OPTION	0
#BITDEF	PS1				OPTION	1
#BITDEF	PS2				OPTION	2
#BITDEF	PSA				OPTION	3
#BITDEF	RTE				OPTION	4
#BITDEF	RTS				OPTION	5
#BITDEF	INTEDG			OPTION	6
#BITDEF	RBPU			OPTION	7
/* EECON1 BITS
#BITDEF	EECON1.RD		EECON1	0
#BITDEF	EECON1.WR		EECON1	1
#BITDEF	EECON1.WREN		EECON1	2
#BITDEF	EECON1.WRERR	EECON1	3
#BITDEF	EECON1.EEIF		EECON1	4
#BITDEF	RD				EECON1	0
#BITDEF	WR				EECON1	1
#BITDEF	WREN			EECON1	2
#BITDEF	WRERR			EECON1	3
#BITDEF	EEIF			EECON1	4
/* --------------------------------------------------------------------

/* page 0
#def	ind0	0x00
#def	tmr0	0x01
#def	pcl		0x02
#def	status	0x03
#def	fsr		0x04
#def	porta	0x05
#def	portb	0x06
#def	eedata	0x08
#def	eeadr	0x09
#def	pclath	0x0A
#def	intcon	0x0B
/* page 1
#def	option	0x81
#def	trisa	0x85
#def	trisb	0x86
#def	eecon1	0x88
#def	eecon2	0x89

/* status bits
#bitdef	status.cary	status	0
#bitdef	status.dc	status	1
#bitdef	status.zero	status	2
#bitdef	status.pd	status	3
#bitdef	status.to	status	4
#bitdef	status.rp0	status	5
#bitdef	status.rp1	status	6
#bitdef	status.irp	status	7
#bitdef	cary		status	0
#bitdef	dc			status	1
#bitdef	zero		status	2
#bitdef	pd			status	3
#bitdef	to			status	4
#bitdef	rp0			status	5
#bitdef	rp1			status	6
#bitdef	irp			status	7
/* intcon bitS
#bitdef	intcon.rbif	intcon	0
#bitdef	intcon.intf	intcon	1
#bitdef	intcon.toif	intcon	2
#bitdef	intcon.rbie	intcon	3
#bitdef	intcon.inte	intcon	4
#bitdef	intcon.toie	intcon	5
#bitdef	intcon.eeie	intcon	6
#bitdef	intcon.gie	intcon	7
#bitdef	rbif		intcon	0
#bitdef	intf		intcon	1
#bitdef	toif		intcon	2
#bitdef	rbie		intcon	3
#bitdef	inte		intcon	4
#bitdef	toie		intcon	5
#bitdef	eeie		intcon	6
#bitdef	gie			intcon	7
/* option bitS
#bitdef	option.ps0		option	0
#bitdef	option.ps1		option	1
#bitdef	option.ps2		option	2
#bitdef	option.psa		option	3
#bitdef	option.rte		option	4
#bitdef	option.rts		option	5
#bitdef	option.intedg	option	6
#bitdef	option.rbpu		option	7
#bitdef	ps0				option	0
#bitdef	ps1				option	1
#bitdef	ps2				option	2
#bitdef	psa				option	3
#bitdef	rte				option	4
#bitdef	rts				option	5
#bitdef	intedg			option	6
#bitdef	rbpu			option	7
/* eecon1 bitS
#bitdef	eecon1.rd		eecon1	0
#bitdef	eecon1.wr		eecon1	1
#bitdef	eecon1.wren		eecon1	2
#bitdef	eecon1.wrerr	eecon1	3
#bitdef	eecon1.eeif		eecon1	4
#bitdef	rd				eecon1	0
#bitdef	wr				eecon1	1
#bitdef	wren			eecon1	2
#bitdef	wrerr			eecon1	3
#bitdef	eeif			eecon1	4
/* --------------------------------------------------------------------






/* General.def  ---- end